Designing Interconnection Buses in VLSI and WSI for Maximum Yield and Minimum Delay

It has been a common practice in recent publications concerned with fault tolerance in VLSI and WSI to assume that interconnection buses can be designed to be almost defect-free by enlarging the width of the lines and the spacing between lines. Although this assumption may be valid in many cases, the cost-effectiveness of this proposed “robust” bus layout is questionable especially in the case of wide buses (e.g., 32 bit wide). In this paper we derive exact expressions for the yield of an interconnection bus as a function of its physical dimensions and the parameters and distribution of the possible open-circuit and short-circuit defects. We also examine the effect of introducing redundancy into the bus and obtain the optimal layout of a given bus (with and without redundancy). Any change in the layout of a bus may affect the propagation delay of the bus and, as a consequence, the performance of the VLSI chip. Hence, the delay of the designed bus in addition to its yield must be taken into account when determining the final layout of the bus. Both yield and delay are discussed in this paper through several numerical examples. Index Terms --Interconnection bus, yield, delay, VLSI, redundancy.